The present invention is directed to a system for and a method of dividing or multiplying a reference frequency signal by a non-integer number while minimizing the introduction of timing jitter to the resultant output frequency signal.
The past several years have witnessed a dramatic increase in the capabilities of high-speed, high-density, broadband data communication systems. Such systems may range anywhere from broadcast or cablecast HDTV systems, local area and wide area network (LAN, WAN) systems, fiber to the home (FTTH) applications and board-to-board interconnections in exchange systems and computers.
In any one of the foregoing applications, it should be noted that bidirectional data communication is in digital form and, accordingly, clock and data recovery circuitry is a key component of the efficient functioning of modern data communications systems. The ability to regenerate binary data is an inherent advantage of transmitting information digitally as opposed to transmitting such information in analog form. However, in order for the intelligence signal to be correctly reconstructed at the receiving end, the transmitted binary data must be regenerated with the fewest possible number of bit errors, requiring low noise and timing jitter (phase noise) at the clock generation source. In high speed data communication systems, low jitters are important for ensuring low error rates.
Clock signal generation is traditionally performed by a Phase-Lock-Loop (PLL) system such as that illustrated in FIG. 1. A PLL operates to compare the frequency and/or phase of an incoming serial datastream to a periodic reference clock signal generated by an oscillator circuit, and to adjust the operational frequency and phase characteristics of the oscillator until its output stream is xe2x80x9clockedxe2x80x9d in both frequency and phase to the data signal. Frequency division and/or frequency multiplication can be used to generate multiple clock phases from a PLL.
FIG. 1 shows a typical PLL circuit that is used to perform a frequency signal multiplication (or division) function. A reference signal (xe2x80x9cINxe2x80x9d) is applied to one input of the Phase/Frequency Detector 10 where the phase and frequency of a feedback clock from a divider circuit 19 is compared. The Phase/Frequency detector 10 circuit outputs signals 16 and 18 to the charge pump circuit 12 indicating whether the feedback clock from the divider circuit is lower or higher in frequency and ahead or behind in phase. The charge pump converts the signals from the Phase/Frequency detector typically into analog current signals that are filtered by the Filter 13. The filtered signal is then output to the Voltage Controlled Oscillator (VCO) 14 which produces an output signal which is typically the output of the PLL (xe2x80x9cOUTxe2x80x9d). The output signal of the VCO is input to the divider circuit 19, which divides the frequency of the output signal by an integer xe2x80x9cNxe2x80x9d in this example. The output signal of the divider circuit is input to the phase detector circuit completing the PLL. In this case, the output signal of the PLL is limited to integer multiples of the reference signal.
Non-integer multiply functions for the overall PLL can be implemented by placing a divider circuit (e.g., divide by D) at the output of the PLL thereby, dividing the output signal by D. This results in FOUT=FINxc3x97N/D, where N/D is a non-integer number. However, when N becomes a large number, The frequency of the VCO may become unpractically large. Non-integer multiply/divide functions can also be implemented by designing the divider circuit 19 of FIG. 1A to appropriately suppress predetermined clock cycles to its input signal at a specific rate defined by a number xe2x80x9cKxe2x80x9d, thereby decreasing its effective divide ratio by K+1/K. FIG. 1B is an exemplary timing diagram for a conventional non-integer division. As shown, every K cycles, one cycle of the OUT signal is suppressed, resulting in K cycles in K+1 periods. Therefore, the frequency of the OUT signal, FOUT=Number of cycles/Time=K/(K+1). T. where T is the period for VCO. Thus, FOUT=FVCOxc3x97K/(K+1), that is dividing FVco by K+1/K.
However, these technique adversely cause large changes in the period of the output of the divider circuit introducing jitter to the output of the PLL. This jitter is as large as the period of the suppressed cycle, i.e., the period of the output signal of the PLL. This large jitter is very undesirable for most systems as described previously.
A non-monolithic implementation that can accomplish this function is commonly known as a VCXO. By applying a control voltage to a VCXO circuit its output signal frequency can be changed, or as commonly referred to, xe2x80x9cpulledxe2x80x9d to a desired frequency in the order of xc2x11000 ppm or less from its natural frequency. However, this implementation is very complex and costly.
Accordingly, prior art-type PLL circuits do not provide an integrated, low-cost, and simple frequency division/multiplication with low jitter. Accordingly, for high-speed PLLs, there is a demonstrated need for a frequency division/multiplication with low jitter which is designed and constructed such that jitters are substantially minimized.
The present invention enables full flexibility to produce frequency multiplication/division by any non-integer output signal frequency (for example, (K+1)/K, or K/(Kxe2x88x921) ) relative to a reference signal frequency, while simultaneously maintaining low jitter performance.
In one embodiment, the invention shifts the phase of the OUT signal by one phase, every K/M cycle. In another embodiment, the invention increases the number of the available clock phases to M and then shifts the phase of the OUT signal by one phase, every K/M cycle. In one aspect of the present invention, this is accomplished by adding a multiplexer (MUX) to the output of the PLL to implement the phase shifting every K/M cycles. In another embodiment, the MUX is placed in the feedback loop of the PLL. In yet another embodiment, a quantizer is used to drive the MUX resulting in further minimization of noise.
In one aspect, the present invention describes an integrated low jitter frequency multiplication/division electronic circuit for multiplying/dividing frequency of a reference signal comprising: a PLL for generating M number of clock phases from the reference signal; and a signal shifter electrically coupled to the PLL for shifting the reference signal by one phase every K/M cycle, wherein (K+1)/K is a divisor number and K/(Kxe2x88x921) is a multiplier number.
In another aspect, the present invention describes a method for multiplying/dividing frequency of a reference signal comprising the steps of generating M number of clock phases; and shifting the reference signal by one phase every K/M cycle, wherein (K+1)/K is a divisor number and K/(Kxe2x88x921) is a multiplier number. In yet another aspect, the present invention describes a frequency division electronic circuit for dividing frequency of a reference signal by a non-integer number (K+1)/K, comprising: PLL for generating M number of clock phases from the reference signal; and a signal shifter electrically coupled to the PLL for shifting the reference signal by one phase every K/M cycle.